External Master Clocks

"A clock is not a component you listen to. It is the timebase every other component depends on to be heard correctly."

Word Clock and Master Clock Are Not the Same Thing

The two terms get used interchangeably in casual conversation, and that habit causes real confusion once someone starts shopping for equipment, so it is worth separating them before going further.

Word clock refers to a specific signal: a square wave running at the audio sample rate itself, 44.1 kHz, 48 kHz, 96 kHz, and so on. Its only job is to mark the exact instant each sample should be latched, and it is normally carried on its own dedicated 75-ohm coaxial line with BNC connectors, standardized in AES11. A word clock signal is meant to be distributed, not generated locally by every device that needs it.

Master clock is the broader term for the reference generator itself, the box that produces a stable timebase for the system to synchronize to. What that box actually outputs varies by design. Some master clock generators output word clock directly, at whatever sample rate the connected devices need. Others output a much higher frequency reference, commonly 10 MHz, which each connected device then uses internally, through its own PLL, to derive whatever word clock or bit clock rate it actually requires.

This distinction matters practically, not just semantically. A device with only a word clock input needs a master clock that can output word clock, at the correct sample rate, and in some cases needs the sample rate switched to match the source material. A device with a 10 MHz reference input is more flexible in one sense, since a single reference frequency serves any sample rate through internal multiplication, but it also means more of the timing-recovery burden sits inside that device's own PLL rather than being handled centrally by the master clock. Neither approach is automatically superior. What matters for sound quality, in both cases, is the same thing this article is about: the stability of the reference itself and the integrity of the cable carrying it, not which of the two signal types is involved.

From here on, "master clock" is used for the reference generator as a device, and "word clock" is used specifically for the sample-rate signal, consistent with how the terms are used through the rest of this site. The impedance behavior of that word clock line is treated in depth in Word Clock Impedance.

The Apparent Contradiction

Ask any competent digital audio engineer where the clock should sit, and the answer is consistent: as close as physically possible to the conversion stage. Short traces, minimal coupling to other circuits, a clean local oscillator feeding the DAC chip directly. This is correct. It is also, on its own, incomplete.

The confusion starts when this design principle, which is true for a single, self-contained device, gets extended into a universal rule that external clocking can never help. It can. Not because the physics of trace length changed, but because an external master clock solves a different problem than local clock quality does. Once a system contains more than one digital source, timing stops being a single-device question and becomes a system-architecture question.

This is the same distinction covered in more depth in Word Clock Impedance and The Digital Hierarchy. Here we go through the mechanism specifically, the different categories of jitter involved, and why the outcome depends entirely on implementation and cable quality, not on the concept alone. For the broader principle of why a signal path has to remain electrically coherent from end to end, see Signal Integrity.

Why Proximity Wins, In Isolation

Take a single DAC with no external inputs to synchronize. Here, putting an excellent local oscillator right next to the conversion stage genuinely is close to optimal.

• The clock trace is short, so there is less length for noise to couple into it.
• There is no connector, no cable, and no external transmission line in the path, so there is nothing to reflect or terminate incorrectly.
• The oscillator can be selected and shielded specifically for that one circuit, with no compromise for driving external loads.

If the only goal is minimizing jitter for one converter chip, this architecture is hard to beat with an external reference bolted on top of it, because the added cable and connector are pure electrical additions. A discontinuity, a length of transmission line, a connector interface that did not exist before. Every one of these is a place where a signal can degrade rather than improve.

This is why "the clock belongs on the board, next to the DAC" is good engineering advice. It is not, however, the whole picture.

Where the Rule Breaks: More Than One Source

The proximity argument assumes a single timing domain. It stops applying the moment a system has to keep two or more devices in step with each other, for example a CD transport feeding a separate DAC, or several digital sources feeding one converter.

In that situation, each device has its own local oscillator, and those oscillators are never identical. Two crystals, even from the same production batch, drift at slightly different rates with temperature, age, and supply variation. Left alone, a transport and a DAC each running their own free clock will slowly diverge in phase, even if both are individually excellent.

The system compensates for this divergence somewhere, and that compensation is itself a source of timing error:

• Asynchronous sample-rate conversion (ASRC) resamples the incoming stream to the DAC's own clock. This solves the drift problem but adds a mathematical resampling stage that can introduce its own artifacts if not implemented cleanly, a tradeoff discussed in The Bit-Perfect Paradox.
• Elastic buffering with reclocking stores incoming data and re-times it to a local clock domain, which recovers timing accuracy at the DAC but does nothing to improve the timing quality of the original transport output, and adds its own PLL behavior to the chain.
• Direct S/PDIF or AES clock recovery extracts timing directly from the incoming data edges. This is convenient, since it needs no extra cable, but it means the DAC's clock quality is now bound to whatever jitter was present on the transport's output plus whatever the interconnect added along the way.

A shared external master clock changes this picture structurally rather than incrementally. Instead of two independent oscillators being reconciled after the fact, both devices are disciplined to the same stable 10 MHz (or similar) reference before they ever generate their working clocks. The transport is no longer generating word clock from its own local timebase and hoping the DAC's recovery circuit tracks it well; both devices derive their sample clock from the same source. This is the point that the "clock next to the DAC" argument does not address, because it was never designed to. Proximity optimizes one device. A shared reference synchronizes several.

The Different Forms of Jitter, and How Each Is Fought

Jitter is not one phenomenon. It is a family of timing errors, each with a different origin, and the origin determines both whether an external reference helps and what actually fixes it.

Random Jitter (Phase Noise)

This is the timing equivalent of noise, small, statistically unpredictable variations in the exact moment a clock edge crosses its threshold. In the frequency domain, this same phenomenon shows up as phase noise, the power spectral density of phase fluctuation around the nominal clock frequency.

Where it comes from: thermal noise in the oscillator circuit itself, and noise on the power supply rail feeding it. These are the two dominant noise mechanisms in almost any clock circuit.

How it is fought: an OCXO (oven-controlled crystal oscillator) holds the crystal at a fixed temperature, which removes the thermally driven component directly at the source rather than filtering it out afterward. A dedicated, well-regulated, low-noise supply for the clock circuit addresses the other half, since a clock oscillator is only as quiet as the rail it runs from.

Periodic Jitter

Timing error that repeats at a fixed rate, producing discrete sidebands around the audio signal at the interfering frequency rather than a smooth noise floor. It is one of the more audible jitter types because it is tonal rather than random, and the ear is comparatively good at detecting periodic modulation.

Where it comes from: coupling from another periodic signal sharing the same chassis or the same reference, most often a switching power supply's fixed switching frequency, a digital control or data line running nearby, or another clock domain bleeding through a shared ground or supply rail.

How it is fought: physical separation and shielding between the clock circuit and switching supplies or digital logic, a clock section fed from its own regulator rather than sharing one with noisy digital circuitry, and, at the receiving end, a PLL loop bandwidth narrow enough to reject disturbances outside the frequencies it actually needs to track. Prevention at the source matters more here than filtering afterward, because a periodic disturbance close in frequency to the clock itself is much harder to remove once it has coupled in.

Data-Dependent Jitter (Deterministic, Pattern-Related)

Also called inter-symbol interference. When a clock or data signal is recovered from a stream whose edge timing depends on the pattern of ones and zeros that came before it, the recovered clock inherits small, pattern-correlated timing shifts.

Where it comes from: clock-embedded interfaces such as S/PDIF, where word clock is recovered from the same line carrying the audio data itself, rather than being distributed on a dedicated line. A band-limited or lossy transmission path makes this worse, since it smears transitions into one another depending on what came before them.

How it is fought: distributing timing on a dedicated word clock or master clock line instead of recovering it from an embedded data stream, which removes the pattern dependency at its root rather than trying to correct for it. Where embedded recovery cannot be avoided, keeping the interconnect's bandwidth and impedance correctly matched limits how much the data pattern is allowed to distort the edges in the first place.

Interface and Reflection-Induced Jitter

Covered in detail in Word Clock Impedance: when a clock signal meets an impedance discontinuity, part of the wave reflects and interferes with later edges, effectively perturbing the position of the threshold crossing.

Where it comes from: this is not a property of the oscillator at all. It is added downstream, at any point where cable, connector, or termination impedance does not match the source and load, for example a 75-ohm cable feeding a 50-ohm input, or a connector geometry that does not match the cable it terminates.

How it is fought: a correctly specified, consistent impedance from source to load, proper termination at the receiving end, and connectors built to match the cable's own geometry rather than a generic fitting. A superior oscillator cannot fix jitter that is introduced after it, on the way to the receiving device, which is why this category is addressed entirely through cable and connector engineering rather than through the clock generator itself.

This last category is the one most relevant to the original question. A better external master clock only delivers a better result at the DAC if the path between the two, cable, connectors, and termination, does not reintroduce as much timing error as the improved oscillator removed.

The Mechanism: What Actually Happens at the PLL

At the receiving device, an incoming reference is almost never used directly. It passes through a phase-locked loop, which is a control system, not a passive wire.

A PLL has a loop bandwidth, a frequency below which it tracks the incoming reference closely, and above which it relies on its own internal, typically quieter, voltage-controlled oscillator instead. This has two consequences that explain why external clocking behaves the way it does in practice:

• Slow variations in the reference (low-frequency phase noise, thermal drift) pass through the PLL and become part of the device's own timing. This is exactly why the long-term frequency stability of the external reference matters. An OCXO's main advantage over a typical internal TCXO is precisely in this low-frequency, close-to-carrier region.
• Fast variations (high-frequency phase noise, interface-induced jitter) are attenuated by the PLL's own filtering, provided the loop bandwidth is set correctly, because the local VCO smooths over rapid fluctuations rather than tracking them.

This is why the effect of an external master clock is described as structural rather than tonal. It does not change frequency response or coloration. It changes the low-frequency stability of the timebase that every sample is measured against, and it does so differently depending on how exposed each device's own clock recovery circuit is, a point covered at the system level in The Ultimate Digital Front End?

The Different Types of Master Clocks

Not every external clock is chasing the same specification, and this is where a lot of marketing material blurs two properties that are genuinely different.

Short-term stability, expressed as phase noise close to the carrier frequency, describes how much a clock's edge timing wanders from one cycle to the next, over intervals of microseconds to a few seconds. This is what a PLL's low-frequency tracking passes straight through, and it is the figure that governs audible jitter.

Long-term stability, expressed in parts per billion (ppb) or parts per trillion (ppt) drift, describes how far the average frequency wanders over hours, days, or years. This matters enormously for telecommunications timing and metrology. For an audio sample clock, it is close to irrelevant, since a sample stream reclocked a few parts per billion off nominal is inaudible as pitch or speed, while the sample-to-sample jitter within that stream is what actually degrades the conversion.

The oscillator technology inside a given clock generator determines which of these two properties it is optimized for, and that is the main reason prices vary as widely as they do.

Figures above are representative ranges for the categories, not a specification for any single product, and the market moves. What stays consistent is the underlying tradeoff: an oven-controlled oscillator is built specifically to minimize the close-to-carrier phase noise that a PLL passes through and that ultimately becomes sample-clock jitter, while a rubidium reference is built to minimize drift over days and months, a property that matters for a telecommunications timebase far more than it does for a stream of audio samples reclocked once every 10 to 20 microseconds.

This is also why some manufacturers, having engineered both, deliberately choose the OCXO route for their flagship reference clock rather than reaching for a rubidium module. It is not a cost-cutting decision, it is an answer to a different question than the one long-term stability actually solves.

The practical implication for a buyer is straightforward: at the entry level, a TCXO-based reference improves on an unclocked source mainly by giving a genuinely stable reference to lock to at all. At the mid and upper tiers, the meaningful comparison between two OCXO-based clocks is their measured close-to-carrier phase noise and the quality of their power supply and shielding, not their headline drift figures. And a rubidium badge on the front panel is not, by itself, evidence of lower audible jitter, since the property it guarantees is not the one a PLL in a DAC or transport is most sensitive to.

Why the Cable Is Not Optional

None of the above works as intended if the physical link carrying the reference reintroduces the very timing error it was meant to remove.

Once clock edge speeds reach the nanosecond range, the connecting cable stops behaving like a simple wire and starts behaving like a transmission line. At that point:

• Characteristic impedance has to be maintained end to end. A 75-ohm word clock cable feeding a 50-ohm reference input, or the reverse, creates a reflection coefficient of roughly 0.2, meaning about 20 percent of the signal voltage reflects back rather than being absorbed cleanly.
• The connector is part of the transmission line, not a passive fitting. A 75-ohm BNC and a 50-ohm BNC look similar but are built to different geometries. Using the wrong one at either end reintroduces a discontinuity regardless of how good the cable itself is.
• Reflections perturb subsequent edges, which shifts the exact moment the receiving circuit registers a threshold crossing. In a clocked system, that shift is, by definition, jitter, added after the master clock generator, not by it.

This is the practical reason an excellent master clock generator can still underperform in a system with the wrong cable, wrong connector, or an impedance mismatch at either end. The oscillator's own phase noise may be extremely low, but the transmission path between it and the receiving device is where a mismatched cable does its damage. A dedicated, correctly specified clock cable is not a tuning accessory in this context. It is the physical layer the entire benefit of the upgrade depends on, and this is the subject covered directly in Impedance Matching and Connectors.

What the Cable Itself Should Be Built From

Because a clock signal's information is entirely in the timing of its edges rather than in its amplitude, the physical build of the cable matters in ways that are easy to overlook next to an audio interconnect, where amplitude and frequency response dominate.

A clock edge is a fast transition, and a fast transition is rich in high-frequency harmonic content, often extending well into the tens or low hundreds of MHz even though the fundamental clock rate itself is only in the kHz to low MHz range. At those frequencies, the construction of the cable directly affects how faithfully the edge arrives:

• A dense, high-coverage braided shield, ideally in two layers rather than one, is what keeps the clock line from picking up radiated interference from nearby switching power supplies, digital logic, or mains wiring. A single loosely woven braid leaves gaps that let high-frequency noise couple straight into the signal.
• A stable, low-loss dielectric, such as PTFE (Teflon), rather than standard PVC, matters because the dielectric constant of the insulation is what sets the cable's characteristic impedance together with its conductor geometry. PVC's dielectric properties drift with temperature and age, which lets the cable's impedance wander away from its nominal value over time. PTFE holds its electrical properties far more consistently, which is precisely what a transmission line carrying a reference clock needs to do for the life of the cable.
• A silver-plated conductor and shield braid address skin effect, the tendency of a fast-edged signal's current to travel mostly at the outer surface of a conductor rather than through its full cross-section. Silver has the highest conductivity of any metal, so plating the copper with it reduces high-frequency resistive loss exactly where a clock edge's harmonic energy concentrates.
• A precision-manufactured BNC interface at each end, rather than a generic crimp connector, keeps the transmission line's impedance continuous right up to the mating point. This is the detail from Connectors that matters most for clock signals specifically: a connector that is a poor geometric match to the cable it terminates reintroduces a discontinuity at exactly the point where the signal leaves the controlled environment of the cable and enters the receiving device.

None of these attributes are about tonal character, because a clock cable does not have one to preserve or distort. They are about holding the transmission line's electrical behavior as close as possible to ideal, for as long as the cable is in service, so that the stability designed into the master clock generator actually reaches the receiving PLL intact.

The Scientific Record

Jitter and its audibility have been studied directly, not just inferred from listening impressions.

Julian Dunn's foundational 1992 AES paper on jitter specification and assessment set out the theoretical framework still used to model jitter's effect on reconstructed audio, showing that sampling-clock jitter produces sidebands around the audio signal whose amplitude depends on both signal level and jitter magnitude, and that the sensitivity to jitter increases with signal frequency.

Benjamin and Gannon's 1998 AES paper, "Theoretical and Audible Effects of Jitter on Digital Audio Quality," remains the most cited controlled study on this question. Their listening tests found audibility thresholds in the range of tens to low hundreds of nanoseconds for random jitter, with the exact figure depending heavily on the test signal, the listener's training, and playback level. Trained listeners using sensitive material detected jitter at substantially lower levels than casual listeners using typical program material.

A later study by Ashihara and colleagues, published in Acoustical Science and Technology in 2005, used a formal two-alternative forced-choice methodology with professional audio engineers and critics and found detection thresholds for sinusoidal jitter components that were, for most subjects and conditions, an order of magnitude below the levels used in typical unblinded demonstrations, though still well above the sub-picosecond figures sometimes claimed in marketing material.

Taken together, this body of work supports a specific, more modest claim than "any jitter is audible": well-implemented digital audio equipment already operates with jitter levels below the more conservative published detection thresholds for random noise-like jitter, which is why the audible differences reported from adding a master clock are usually described as changes in low-level continuity, spatial stability, and reverberation decay rather than gross tonal shifts.

That description is consistent with jitter's known mechanism, since jitter manifests as modulation noise and sidebands around the signal rather than as a change in frequency response. It also explains why periodic and interface-induced jitter, the deterministic types described above, tend to be reported as more audible at lower amplitudes than random jitter, since deterministic sidebands are tonal and therefore easier for the ear to isolate from the program material than a broadband noise floor is.

The Transport Case, Specifically

The original example, a CD transport with a dedicated external clock input, is close to the best-case scenario for this upgrade, for a structural reason rather than a subjective one.

A transport has to recover, generate, and output a stable digital stream from a mechanically active environment, a spinning disc, a servo system correcting for eccentricity, all of it happening in real time next to the clock circuit. Its output clock is, in that sense, less insulated from real-world variability than a DAC's internal reclocking stage typically is. Feeding it a shared, ultra-stable external reference replaces a locally generated oscillator, subject to exactly this mechanical and electrical activity, with a common timebase that the downstream DAC is also referenced to.

This is also precisely the case where the local-clock-proximity argument does not apply, because the goal is no longer "make one device's own clock as good as possible." The goal is to remove the transport and the DAC from two independent, drifting timing domains and put them into one shared, synchronous domain. A local clock on the transport board, however good, cannot do that on its own. Only a common reference, correctly cabled to both ends, can.

Bottom Line

Keeping the clock close to the conversion stage is correct engineering practice for a single, self-contained device, because it minimizes trace length and avoids adding an external transmission line where none needs to exist.

An external master clock addresses a different problem: keeping multiple devices, such as a transport and a DAC, in the same stable timing domain instead of reconciling two independently drifting oscillators after the fact. The mechanism runs through the receiving device's PLL, which tracks the reference's low-frequency stability while filtering high-frequency noise, so the benefit is structural rather than tonal.

None of this works if the cable and connectors between the master clock and the receiving devices are not correctly specified for the impedance and edge speeds involved. A mismatched cable can reintroduce, through reflections, exactly the kind of timing error the upgrade was meant to remove. That is a construction question as much as a specification question: dense double-braid shielding, a stable low-loss dielectric such as PTFE, silver-plated conductors to manage skin-effect loss at the harmonic frequencies a fast clock edge contains, and a precision BNC interface at each end, all decide whether the transmission line holds its intended impedance for the life of the cable or drifts away from it. The oscillator, the implementation at the receiving PLL, and the cable, built correctly and staying correct over time, are three parts of the same chain, and the improvement only shows up at the listening seat when all three are addressed together.

Conclusion

The proximity rule and the external clock argument were never actually in conflict. They answer different questions, and the mistake is treating one design principle as if it were universal.

Keep the clock close to the conversion stage when there is only one clock to worry about. That is still correct, and no external reference changes it. But the moment a system has to keep two or more devices, a transport and a DAC, several sources feeding one converter, in the same timing domain, the question stops being about trace length on one board and becomes a question of shared reference, PLL behavior, oscillator technology, and the electrical integrity of the path connecting them.

None of those four elements works in isolation. An OCXO with excellent close-to-carrier phase noise delivers nothing if the receiving PLL's loop bandwidth is poorly chosen. A well-chosen loop bandwidth delivers nothing if the cable between the two devices reflects and reintroduces the timing error the oscillator was built to remove. And the cable itself only holds its intended impedance for the life of the installation if it is actually built for the job, dense shielding, a stable dielectric, low-loss conductors, connectors that match the transmission line rather than interrupting it.

That is the practical shape of the answer to the original question. A superior external master clock, correctly cabled into a system with more than one digital source, is not a violation of good engineering practice. It is good engineering practice, applied one level up, from the single device to the system it lives in.